High speed sense amplifier

ABSTRACT

A high-speed sense current amplifier with a low power consumption for a memory cell, the sense current amplifier having: a first current mirror circuit, which amplifies a memory signal current received from the memory cell via a memory signal line and outputs it at a signal output of the sense current amplifier; a second current mirror circuit, which generates a setting current in a manner dependent on the received memory signal current; and an adjustable reference current source, which outputs a reference current to the signal output of the sense current amplifier, the magnitude of the output reference current being set, via a setting line, in a manner dependent on the setting current generated by the second current mirror circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a high-speed sense current amplifier with a lowpower consumption for a memory cell.

2. Description of the Related Art

Semiconductor memories are binary data memories in which the individualmemory cells SZ are arranged in matrix form and comprise semiconductorcomponents, in particular transistors. In this case, the memory cells SZare connected to word lines WL and bit lines BL, running perpendicularlythereto. The matrix contains n*m memory cells. The addressing, i.e. theselection of a memory cell SZ or a memory word, is effected byactivation of the word lines WL. In this case, the addressing isperformed by an address decoder which, given n external address lines,internally generates 2^(n) selection signals for word line and bit lineselection. The data information items contained in the memory cells SZare read out via a sense amplifier.

FIG. 1 schematically shows the construction of a semiconductor memoryarrangement. The address decoder D is connected to an address bus AR anddecodes the addressing signal present on the address bus AR for theselection of memory cells SZ within the semiconductor memory. Theread-out data contained in the memory cells SZ pass via memory signallines to a multiplexer MUX, which is connected to the sense amplifier onthe output side. The sense amplifier amplifies the received memorysignal and outputs it to a data bus DR via an output buffer P.

FIG. 2 schematically shows part of a sense current amplifier for theread-out and amplification of the data content contained in a memorycell SZ, according to the prior art.

The memory cell SZ contains a data bit information item, the memory cellSZ being in a logic low state L(low) or a logic high state H(high). Thememory cell SZ may be a RAM memory cell or a ROM memory cell. The memorycell SZ is addressed via a word line WL leading away from the decoder Dand outputs the data content contained in it via the bit line BL. Inthis case, a memory signal current I_(BL) flows via the memory signalline or bit line BL to the multiplexer MUX. The memory signal currentI_(BL) is zero if the memory cell SZ is in a logic low state L. If thememory cell SZ is in a logic high state H, a predetermined memory signalcurrent I_(BL) flows. The bit line BL has a line capacitance and can beprecharged or recharged via a charging circuit comprising e.g. a clockedMOSFET transistor. The multiplexer MUX is controlled in a mannerdependent on a selection signal SS1 and through-connects the memorysignal line BL to the input E of the sense current amplifier LSV. Thesense current amplifier LSV contains a current mirror circuit which issupplied with a supply voltage V_(DD). On the output side, the currentmirror circuit is connected to a node which is connected to the output Aof the sense current amplifier LSV according to the prior art. Thecurrent mirror circuit amplifies the memory signal current I_(BL)received via the input E with a constant factor K and outputs theamplified current K·I_(BL) at the output A of the sense currentamplifier LSV. Furthermore, at a reference current source terminal REF,a reference current source is connected to the current node connected tothe output A. The reference current source according to the prior art islikewise connected to the supply voltage V_(DD) and can be selected bymeans of a selection signal SS2. The summation current node has anintrinsic capacitance C_(A).

FIG. 3 shows the reference current source according to the prior art asillustrated in FIG. 2. The reference current source contains a pluralityof N-MOSFET transistors T1, T2, and T3. The N-MOSFET transistor T1 ofthe reference current source generates a constant current in a mannerdependent on the selection signal SS2. If the selection signal SS2 islogic 0, the constant current I_(K) of the MOSFET transistor T1 is zero.Conversely, if the selection signal SS2 is switched on, a constantcurrent I_(K)ø with a specific constant current magnitude flows throughthe N-MOSFET transistor T1. The following hold true:

I _(K)=0 if SS 2=1

I _(K) =I _(Kø) if SS 2=ø  (1)

The reference current source according to the prior art furthermorecontains a current mirror circuit comprising the two N-MOSFETtransistors T2 and T3, the two gate terminals of the two N-MOSFETtransistors T2 and T3 being connected to one another and having a directconnection to the source terminal of the N-MOSFET transistor T1. Theconstant current I_(Kø) is mirrored by the current mirror circuit T2 andT3, the current gain being determined by the current channelwidth/length ratio W/L of the two transistors T2 and T3.

The N-MOSFET T2 of the current mirror circuit has a source terminalconnected to ground and a drain terminal connected to the referencecurrent terminal REF. The current mirror circuit T2 and T3 generates aconstant reference current I_(REFø) at the reference current terminalREF, the following holding true: $\begin{matrix}{I_{{REF}\quad \varnothing} = {\frac{\mu \quad {Cox}\quad {W/L}}{2}\left( {V_{GS} - V_{T}} \right)^{2}}} & (2)\end{matrix}$

where:

W/L is the channel width/length ratio of the transistor T2,

C_(ox) is the capacitance of the dielectric,

V_(T) is the threshold voltage of the transistor T2, and

V_(GS) is the gate/source voltage of the transistor T2.

Since the voltage V_(GS) between the gate and the source of thetransistor T2 is constant and the remaining quantities are alsopredetermined, the reference current I_(REFO) generated by the referencecurrent source is constant.

FIG. 4 shows the current mirror circuit contained in the sense currentamplifier according to the prior art. The current mirror circuitcontains two P-MOSFETs T4 and T5, whose gate terminals are connected toone another and are connected to the input E of the current mirrorcircuit. The two drain terminals of the two P-MOSFETS T4 and T5 areconnected to the supply voltage potential V_(DD). The source terminal ofthe first P-MOSFET T4 is likewise connected to the signal input E of thecurrent mirror circuit and receives the memory signal current I_(BL).The channel width/length ratios W/L of the two P-MOSFETs T4 and T5 aredefined in such a way that the memory signal current I_(BL) is outputamplified by a fixed gain factor K at the source terminal of the secondP-MOSFET T5.

In the conventional sense current amplifier, as illustrated in FIG. 2,the following holds true for the output voltage at the output A:

VA=VDD if K*I _(BL) ≧I _(REFø)

VA=ø if K*I _(BL) <I _(REFø)  (3)

In the conventional sense current amplifier according to the prior art,as illustrated in FIG. 2, one disadvantage is that a high reading speedfor the readout of the memory cell SZ and a low power consumption P ofthe sense current amplifier LSV cannot be achieved simultaneously. Thiswill be explained below with reference to the signal profile illustratedin FIG. 5. If the memory cell SZ is not being read, the output A of thesense current amplifier LSV is at a predetermined high potentialcorresponding to the supply voltage V_(DD). If the memory cell SZ is notbeing read, the memory signal current I_(BL) is 0.

At the instant t₁, a read operation A is initiated in the exampleillustrated in FIG. 5, in the course of which a memory cell SZ which isin a logic low state L is read. When reading from a memory cell SZ whichassumes a logic low state L, a memory signal current I_(BL) of zero isgenerated, so that an output current of K*I_(BL) which is lower than theconstant reference current I_(REPø) flowing into the reference currentsource is also output at the output of the current mirror circuit. Sincethe reference current I_(REFO) flowing from the current node is greaterthan the amplified memory signal current (K*I_(BL)) flowing into thecurrent node A, the intrinsic or parasitic capacitance C_(A) at theoutput A of the sense current amplifier LSV according to the prior artis discharged, so that the output voltage V_(A) at the output A of thesense current amplifier falls, as is illustrated in FIG. 5.

The discharge process at the output A of the sense current amplifier LSVtakes place more quickly the higher the constant reference currentI_(REFO). The discharge process lasts for a relatively long time in thecase of a relatively low reference current I_(REFOA) while the dischargeprocess takes place quickly in the case of a relatively high referencecurrent I_(REFC).

For the discharge time τ of the intrinsic capacitance C_(A) at theoutput A of the sense current amplifier LSV according to the prior art,the following therefore holds true to an approximation:

τ≅V _(DD) /I _(REFø) *C _(A)  (4)

The faster the discharge process takes place at the 5 output A of thesense current amplifier LSV, the higher the read-out speeds that can beachieved by means of the semiconductor memory.

At the instant t₂, the read operation A is ended and the output node Aof the sense current amplifier is charged again. At the instant t₃, afurther read operation B is initiated, in the course of which the memorycell SZ is this time read in a logic high state H. In this state, thememory cell SZ yields a memory signal current I_(BL) of predeterminedmagnitude which is amplified by the current mirror circuit. Since theamplified signal current K*I_(BL) is greater than the constant referencecurrent I_(REFO), the output voltage VA at the output A of the sensecurrent amplifier, in accordance with equation (3), is V_(A)=V_(DD).

The following problem area exists in the case of the conventional sensecurrent amplifier LSV, as illustrated in FIG. 2. The higher the constantreference current I_(REFO), the shorter the discharge time τ and theshorter the possible read-out times of the memory. However, this has theresult that, in accordance with equation (3), the current gain K throughthe current mirror circuit must be high enough, when reading from amemory cell SZ which is in a logic high state, to satisfy the inequalitycondition and to switch reliably to the high voltage potential V_(DD) atthe output A. However, a high gain factor K of the current mirrorcircuit is equivalent to a high power loss P of the sense currentamplifier LSV. The high power loss P entails a number of disadvantages.The higher the power loss P, the higher the temperature T generated bythe sense current amplifier LSV, thus necessitating cooling devices,under certain circumstances. Furthermore, wider power supply linesbecome necessary in an integrated sense current amplifier LSV, in orderto achieve the required power. A further disadvantage is that, in thecase of battery-operated sense current amplifiers LSV, the batterieshave to be recharged at shorter time intervals. This has considerabledisadvantages in particular in the case of portable devices containingsemiconductor memories, such as e.g. portable telephones.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a sensecurrent amplifier which, on the one hand, enables a high speed whenreading from a semiconductor memory and at the same time has a low powerconsumption.

The invention provides a high-speed sense current amplifier with a lowpower consumption for a memory cell, the sense current amplifier having:a first current mirror circuit, which amplifies a memory signal currentreceived from the memory cell via a memory signal line and outputs it ata signal output of the sense current amplifier; a second current mirrorcircuit, which generates a setting current in a manner dependent on thereceived memory signal current; and an adjustable reference currentsource, which outputs a reference current to the signal output of thesense current amplifier, the magnitude of the output reference currentbeing set, via a setting line, in a manner dependent on the settingcurrent generated by the second current mirror circuit.

Preferred embodiments of the high-speed sense current amplifieraccording to the invention are described below with reference to theaccompanying figures for elucidating features that are essential to theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a conventional semiconductor memoryarrangement according to the prior art;

FIG. 2 shows a circuit diagram with a sense current amplifier LSVaccording to the prior art;

FIG. 3 shows a reference current source contained in the sense currentamplifier LSV illustrated in FIG. 2, according to the prior art;

FIG. 4 shows a current mirror circuit contained in the sense currentamplifier LSV illustrated in FIG. 2, according to the prior art;

FIG. 5 shows a signal timing diagram for elucidating the problem area onwhich the invention is based;

FIG. 6 shows a circuit diagram with a high-speed sense current amplifieraccording to the invention;

FIG. 7 shows an adjustable reference current source contained in thesense current amplifier according to the invention as illustrated inFIG. 6; and

FIG. 8 shows the current mirror circuits contained in the sense currentamplifier according to the invention as illustrated in FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description of the preferred developments of the inventionare provided without limitation to the claims.

In preferred developments of the invention, the first and second currentmirror circuits of the high-speed sense current amplifier according tothe invention are preferably connected to the memory signal line inparallel with one another. In this case, the two current mirror circuitsare preferably each constructed from two MOSFETs whose gate terminalsare connected to one another.

In a preferred embodiment of the high-speed sense current amplifier, thefirst current mirror circuit has a first MOSFET whose gate terminal andwhose source terminal are connected to the memory signal line and whosedrain terminal is connected to a supply voltage, and has a secondMOSFET, whose gate terminal is connected to the gate terminal of thefirst MOSFET, whose drain terminal is connected to the supply voltageV_(DD) and whose source terminal is connected to the signal output ofthe sense current amplifier.

In a preferred embodiment of the high-speed sense current amplifier, thesecond current mirror circuit has a first MOSFET, whose gate terminaland whose source terminal are connected to the memory signal line andwhose drain terminal is connected to a supply voltage V_(DD), and has asecond MOSFET, whose gate terminal is connected to the gate of the firstMOSFET, whose drain terminal is connected to the supply voltage, V_(DD)and whose source terminal is connected to the setting line foroutputting the setting current.

The adjustable reference current source of the sense current amplifierpreferably has a current mirror circuit for the adjustable amplificationof a constant current, the current mirror circuit having a first MOSFET,whose drain terminal is connected, at a reference current sourceterminal of the reference current source for outputting an amplifiedadjustable reference current, to the signal output of the sense currentamplifier, whose source terminal is connected, at a setting terminal ofthe reference current source, to the setting line for receiving thesetting current, and whose gate terminal is connected to a gate terminalof a second MOSFET of the current mirror circuit.

The adjustable reference current which can be output by the referencecurrent source is preferably set in a manner dependent on the settingcurrent received via the setting terminal.

In this case, the received setting current is preferably used to set thevoltage V_(GS) between the gate terminal and the source terminal of thefirst MOSFET of the current mirror circuit within the reference currentsource for the alteration of the adjustable reference current.

The output of the sense current amplifier preferably has a capacitance.

In a particularly preferred embodiment of the sense current amplifier,the signal output has a signal buffer circuit.

In a further preferred embodiment of the sense current amplifier, thememory signal line has a controlled multiplexer for switching the memorysignal current through to the two current mirror circuits of the sensecurrent amplifier.

The memory signal line is preferably connected to a charging circuit forcharging or recharging the memory signal line.

The memory cell is a RAM memory cell or ROM memory cell.

With reference to FIG. 1, a memory cell 1 is addressed by an addressdecoder (not illustrated) via a word line 2 and outputs a memory signalcurrent via a memory signal line or bit line 3. The memory signal line 3is connected via a line 4 to a charging circuit 5 for charging orrecharging the memory signal line 3. The memory signal line 3 isconnected to an input 6 of a multiplexer circuit 7, which can becontrolled via a control line 8 for through-connecting the memory signalline 3 to an output line 9 of the multiplexer circuit 7. The line 9 isconnected to a signal input 10 of the high-speed sense current amplifier11. The signal input 10 of the high-speed sense current amplifier 11 isconnected via an internal line 12 to a signal input 13 of a currentmirror circuit 14. The current mirror circuit 14 is supplied with asupply voltage V_(DD) via a supply voltage line 15. The current mirrorcircuit 14 has a current output 16, via which the current mirror circuit14 outputs the memory signal current I_(BL) received at the signal input13, after having amplified the current, to a current node 18 via a line17. The current node 18 is connected to a signal output 20 of the sensecurrent amplifier 11 via an internal output line 19 of the sense currentamplifier 11. The current node 18 is furthermore connected via a line 21to a reference current source terminal 22 of an adjustable referencecurrent source 23. The adjustable reference current source 23 isconnected to the supply voltage V_(DD) via a supply voltage line 24. Theadjustable reference current source furthermore has a grounding line 25connection to ground GND. The adjustable reference current source 23receives a selection signal SS2 via a control line 26.

The current mirror circuit 14 has an output terminal 27, which isconnected via a setting line 28 to a current setting input 29 of thereference current source 23. Via the setting line 28, the current mirrorcircuit 14 sets the magnitude of the reference current ref output by thereference current source 23 at the reference current source terminal 22.

The output 20 of the sense current amplifier 11 is connected to a databuffer 22 via an output line 21. The data buffer 22 preferably comprisesa series circuit of inverter gates. The data buffer 22 has an outputline 23—for connection to an internal data bus.

The summation current node 18 connected to the signal output 20 of thesense current amplifier 11 has an intrinsic capacitance of 30.

FIG. 7 shows in detail the adjustable reference current source 23illustrated in FIG. 6. The adjustable reference current source 23contains five N-MOSFETs 31, 32, 33, 34, and 35. The gate terminal of theMOSFET 31 is controlled by the selection signal SS2 via a line 36. Thesource terminal of the MOSFET 31 is supplied with the supply voltage VDDvia a line 37. The drain terminal of the MOSFET 31 is connected to thesource terminal of the MOSFET 33 via a line 38. The two gate terminalsof the MOSFET5 32, 33 are connected to one another via a connecting line39. In this case, the two lines 38 and 39 are short-circuited via a line40. The source terminal of the MOSFET 32 is connected to the referencecurrent source terminal 22 via a line 41. The source terminal of theMOSFET 34 is connected to the drain terminal of the MOSFET 32 via a line42. The line 42 which connects the two MOSFETS 32 and 34 to one anotheris connected to the setting terminal 29 of the reference current source23 at a node 43 via a line 44. The drain terminal of the MOSFET 34 isconnected to ground via a line 45. The two gate terminals of the MOSFETs34 and 35 are connected to one another via a connecting line 46, whichis connected, at a node 47, via a line 48 to a control terminal 49 forapplication of a selection signal SS3. The drain terminal of the MOSFET35 is likewise connected to ground via a grounding line 50. The sourceterminal of the MOSFET 35 is connected to the drain terminal of theMOSFET 33 via a line 51.

If the selection signal SS2 is logic high, the MOSFET 31 is turned onand generates a constant current I_(K), which is mirrored by a currentmirror circuit. In this case, the current mirror circuit 52 of theadjustable reference current source is formed by the two MOSFETs 32 and33. The reference current I_(REF) taken up at the reference currentsource terminal 22 is set in a variable manner dependent on the settingcurrent I_(SETTING) captured at the setting terminal 29.

The following holds true: $\begin{matrix}{{I_{REF}\left( V_{GS32} \right)} = {\frac{\mu \quad {Cox}\quad {W/L}}{2}\left( {V_{GS32} - V_{T32}} \right)^{2}}} & (5)\end{matrix}$

The adjustable reference current I_(REF) output by the reference currentsource 23 depends on the gate/source voltage across the MOSFET 32.

If the selection signal SS3 is on, as the setting current I_(SETTING)increases, the gate/source voltage V_(GS32) across the MOSFET 32decreases and the reference current I_(REF) generated at the referencecurrent terminal 22 falls.

Consequently, the following holds true:

I _(REF) =I _(REF)(I _(SETTING))  (6)

The gain ratio with which the constant current IK is mirrored afterhaving been amplified by the current mirror circuit 52 is defined by thechannel width/length ratio (W/L) of the MOSFET transistors 32 and 33.Typical gain factors M lie in a range of 1-10.

FIG. 8 shows in detail the current mirror circuit 14 according to theinvention as illustrated in FIG. 6. The current mirror circuit 14receives, via the signal 10 input 13, the memory signal current outputby the memory cell 1 and is supplied with the supply voltage V_(DD) viathe voltage supply line 15. The current mirror circuit 14 furthermorehas a current output 16 for outputting an amplified memory signalcurrent and a setting output terminal 27 for outputting a settingcurrent I_(SETTING). The current mirror circuit 14 contains threeP-MOSFETs 53, 54 and 55. The drain terminal of the P-MOSFET 53 isconnected via a line 56 to the signal input 13 of the current mirrorcircuit 14. The two gate terminals of the MOSFETs 53, 54 are connectedto one another via a connecting line 57. At a potential node 58, theconnecting line 57 between the two P-MOSFETs 53 and 54 is connected tothe line 56 at a branching node 60 via a line 59. The node 58 isfurthermore connected to the gate terminal of the P-MOSFET 55 via a line61. The source terminals of the P-MOSFETs 53, 54 and 55 are connectedvia voltage supply lines 62, 63 and 64 to a node 65, which is connectedto the supply voltage V_(DD) via a line 66. The drain terminal of theP-MOSFET 54 is connected via a line 67 to the setting output terminal 27of the current mirror circuit 14. The drain terminal of the P-MOSFET 55is connected via a line 68 to the current output terminal 16 of thecurrent mirror circuit.

The current mirror circuit 14 according to the invention as illustratedin FIG. 8 contains a first current mirror circuit, formed by the twoP-MOSFETs 53, 55, and a second current mirror circuit, formed by the twoP-MOSFETs 53, 54. The first current mirror circuit 53 and 55 amplifiesthe memory signal current I_(BL) output by the memory cell 1 via thememory signal line 3 with a gain factor K and outputs the amplifiedmemory signal current at the current output 16.

The second current mirror circuit 53 and 54 generates a setting currentI_(SETTING) in a manner dependent on the memory signal current I_(BL)received at the signal input13. For this purpose, the reception thememory signal current is amplified with a gain H.

The following holds true:

I _(SETTING) =H*I _(BL)  (7)

The two gain factors K and H can be defined by the channel width/lengthratios of the P-MOSFET transistors 53, 54 and 55.

If, during a memory read operation B, the memory signal current I_(BL)is high when reading out a logic high state in the memory cell 1, thesetting current I_(SETTING) is likewise high. The high setting currentI_(SETTING) is fed via the setting line 28 to the setting terminal 29 ofthe controllable reference current source 23, so that the gate/sourcevoltage V_(GS) between the gate terminal and the source terminal of theN-MOSFET 32 decreases. Consequently, in accordance with equation (5),the adjustable reference current I_(REF) decreases as the gate/sourcevoltage decreases. Therefore, in the sense current amplifier 11according to the invention, the power loss P is low during the readoperation B (as is illustrated in FIG. 5) and on account of thereference current I_(REF) that is set low.

Conversely, if a low signal memory current I_(BL) is read from thememory cell 1 during the memory read operation A, the setting currentI_(SETTING) decreases in accordance with equation (7) and thegate/source voltage at the MOSFET 32 within the controllable referencecurrent source 23 rises. In accordance with equation (5), the setreference current I_(REF) output by the controllable reference currentsource 23 likewise rises as a result of this. On account of the risingreference current I_(REF), the required memory read-out time decreasesconsiderably as the discharge time τ falls, in accordance with equation(4). As a result, it is possible to achieve considerably higher read-outspeeds for reading from the semiconductor memory.

The sense current amplifier 11 according to the invention enables atleast a doubling of the read-out speed for reading from the memory cell1 of a semiconductor memory.

The drain and source terminals (D, S) of the MOSFETs illustrated inFIGS. 7 and 8 are interchangeable.

The high-speed sense current amplifier 11 according to the inventionwith a low power consumption for a memory cell 1 guarantees a highchangeover speed at the output of the sense current amplifier in thecase of the read operation A (see FIG. 5), i.e. for a low memory signalcurrent read out, on account of the high reference current I_(REF) and alow power consumption P in the case of a read operation B, i.e. in theevent of a high memory signal current on account of the referencecurrent I_(REF) set low, since the value of the reference current isadapted to the to the value of the memory signal current. Consequently,there is no need to increase the mirror gain K.

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art.

What is claimed is:
 1. A high-speed sense current amplifier with a lowpower consumption for a memory cell, comprising: a first current mirrorcircuit which amplifies a memory signal current received from the memorycell via a memory signal line and outputs it at a signal output of thesense current amplifier; a second current mirror circuit which generatesa setting current dependent on the memory signal current received fromthe memory cell; and an adjustable reference current source whichoutputs a reference current to said signal output of the sense currentamplifier, a magnitude of the reference current being set via a settingline dependent on the setting current generated by said second currentmirror circuit.
 2. A high-speed sense current amplifier according toclaim 1, wherein said first current mirror circuit and said secondcurrent mirror circuit are connected to said memory signal line inparallel with one another.
 3. A high-speed sense current amplifieraccording to claim 1, wherein said first and second current mirrorcircuits each include two MOSFETS whose gate terminals are connected toone another.
 4. A high-speed sense current amplifier according to claim1, wherein said first current mirror circuit includes a first MOSFETwhose gate terminal and whose source terminal are connected to saidmemory signal line and whose drain terminal is connected to a supplyvoltage, and said first current mirror circuit includes a second MOSFETwhose gate terminal is connected to said gate terminal of said firstMOSFET and whose drain terminal is connected to the supply voltage andwhose source terminal is connected to said signal output of the sensecurrent amplifier.
 5. A high-speed sense current amplifier according toclaim 4, wherein said setting current is used to set a voltage betweensaid gate terminal and said source terminal of said first MOSFET of saidfurther current mirror circuit within the reference current source foramplifying the reference current.
 6. A high-speed sense currentamplifier according to claim 1, wherein said second current mirrorcircuit includes a first MOSFET whose gate terminal and whose sourceterminal are connected to said memory signal line and whose drainterminal is connected to a supply voltage, and said second currentmirror circuit includes a second MOSFET whose gate terminal is connectedto said gate terminal of said first MOSFET and whose drain terminal isconnected to the supply voltage and whose source terminal is connectedto said setting line for outputting the setting current.
 7. A high-speedsense current amplifier according to claim 1, wherein said adjustablereference current source includes a further current mirror circuit forthe adjustable amplification of a constant current, said further currentmirror circuit having a first MOSFET whose drain terminal is connectedat a reference current source terminal of said reference current sourcefor outputting an amplified adjustable reference current to said signaloutput of the sense current amplifier and whose source terminal isconnected at a setting terminal of said reference current source to saidsetting line for receiving the setting current and whose gate terminalis connected to a gate terminal of a second MOSFET of the current mirrorcircuit.
 8. A high-speed sense current amplifier according to claim 1,wherein the adjustable reference current which is output by saidreference current source is set dependent on the setting currentreceived via said setting terminal.
 9. A high-speed sense currentamplifier according to claim 1, wherein said signal output of thehigh-speed sense current amplifier has a capacitance.
 10. A high-speedsense current amplifier according to claim 1, further comprising: asignal buffer circuit at said signal output of the high-speed sensecurrent amplifier.
 11. A high-speed sense current amplifier according toclaim 1, further comprising: a controlled multiplexer at said memorysignal line has for switching the memory signal current through to saidfirst and second current mirror circuits of the high-speed sense currentamplifier.
 12. A high-speed sense current amplifier according to claim1, further comprising: a charging circuit connected to said memorysignal line for charging or recharging said memory signal line.
 13. Ahigh-speed sense current amplifier according to claim 1, wherein saidmemory cell is a RAM memory cell.
 14. A high-speed sense currentamplifier according to claim 1, wherein said memory cell is a ROM memorycell.